Semiconductor etching is one of the most fundamental subtractive manufacturing processes within integrated circuit (IC) fabrication. After photolithography prints circuit patterns on photoresist coated wafers, etching selectively removes the exposed thin-film material, permanently transferring the circuit layout onto the wafer substrate. This step defines transistors, interconnects, vias, pads and all micro/nano structures inside a finished semiconductor chip.

Two primary etching categories dominate IC manufacturing: wet etching and dry (plasma) etching. Manufacturers select the suitable etching method based on feature size, material type, required sidewall profile, selectivity and production throughput.

Process Workflow

1. Photolithography patterning: A photoresist layer is coated, exposed and developed on the wafer to form a protective mask with predefined circuit patterns.
2. Pre-etch cleaning: Wafer surface cleaning removes particles, organic contaminants and residual residues to avoid etching defects.
3. Etch execution:
   • Wet etching: Immerse wafer into liquid chemical etchant; chemical reaction dissolves unmasked material, typically isotropic with side undercut.
   • Dry plasma etching: Vacuum chamber with reactive gas, RF power generates plasma. Combined chemical reaction and ion physical bombardment remove material, creating anisotropic vertical sidewalls.
4. Etch endpoint detection: Monitor optical or spectral signals to judge when target layer is fully removed and stop etching promptly.
5. Post-etch treatment: Residue removal, photoresist stripping and wafer cleaning to eliminate etching byproducts.
6. Inspection & metrology: Measure critical dimension (CD), sidewall angle and check for defects before next fabrication step.

Core Advantages

• Precise pattern transfer: Convert photomask design into physical micro/nano circuit structures on silicon wafers.
• Dual process options: Wet etching for high-volume, low-cost larger features; dry plasma etching for ultra-fine nanoscale geometries.
• Tunable material selectivity: Etch one thin film layer while keeping underlying layers intact, protecting sensitive device structures.
• Controllable etch profile: Switch between isotropic (horizontal + vertical removal) and anisotropic (vertical-only) profiles for different device requirements.
• Scalable for different nodes: Works for mature large-node ICs, MEMS devices, and advanced sub-10nm logic & memory chips.

Application Fields

• Logic IC production: Microprocessor, MCU, FPU transistor and interconnect patterning.
• Memory chips: DRAM, NAND Flash channel and trench structure fabrication.
• Semiconductor packaging: RDL redistribution layer, silicon interposer, bump opening etching.
• MEMS sensors: Accelerometers, gyroscopes, pressure sensors micro-structuring.
• Optoelectronic chips: Image sensors, VCSEL, LED wafer thin film patterning.

Design & Process Considerations

• Critical dimension (CD) control is the top priority; tiny CD deviation directly impacts chip performance and yield.
• Material matching: Etch chemistry must be customized for silicon, silicon oxide, silicon nitride, aluminium, copper and other thin films.
• Sidewall profile requirement: Fine features demand anisotropic dry etching; larger structures may use cost-effective wet etching.
• Defect control: Particles, undercut, over-etching or under-etching will cause circuit short/open failures.
• Cost & throughput trade-off: Wet etching offers higher throughput and lower capital cost; dry plasma etching delivers higher precision but requires expensive vacuum equipment.