Dry etching, also widely known as plasma etching, is a critical semiconductor fabrication technique that removes thin-film material from silicon wafers without liquid chemical solutions. Unlike wet chemical etching which relies on liquid etchants and often delivers isotropic undercut, plasma dry etching uses energized reactive gas plasma to achieve highly controlled, anisotropic vertical sidewalls for ultra-fine semiconductor features.

Process Workflow

1. Wafer preparation and loading: The patterned photoresist-coated wafer is placed inside a vacuum etching chamber.
2. Chamber evacuation: The system pumps down to maintain low-pressure vacuum conditions to stabilize plasma.
3. Process gas injection: Specific reactive gases are introduced based on target materials (silicon, oxide, metal, nitride).
4. Plasma generation: Radio frequency (RF) power ionizes the gas to form plasma, containing reactive radicals and energetic ions.
5. Selective material removal: Chemical reaction between radicals and wafer material, combined with physical ion bombardment, etches exposed areas. Ions travel vertically under electric field, creating steep sidewalls.
6. Chamber purging & wafer unloading: Residual gas and byproducts are pumped out; the etched wafer is removed for subsequent steps like stripping photoresist.

Core Advantages

• Anisotropic etching profile: Creates near-vertical sidewalls with minimal undercut, essential for nanoscale transistor and interconnect structures.
• Ultra-high resolution: Supports sub-nanometer and micron-level feature precision, suitable for advanced node chips.
• Excellent material selectivity: Tunable gas chemistry allows selective etching of one layer while preserving underlying thin films.
• Controllable etch depth: Precise endpoint detection monitors etch depth and stops etching once target thickness is reached.
• Low wafer contamination: No liquid residues compared to wet etching, reducing particle defects for high-yield semiconductor manufacturing.

Application Fields

• Advanced IC manufacturing: FinFET, GAA transistor definition at 7nm, 5nm and smaller process nodes.
• MEMS & microfluidic devices: Fabricate deep micro trenches, channels and micro structures on silicon wafers.
• Semiconductor packaging: Etch redistribution layers (RDL), silicon interposers and mask openings.
• Display industry: Thin-film etching for OLED and LCD backplane circuits.
• Optical components: Pattern optical masks and micro-optics on quartz or silicon substrates.

Design & Process Considerations

• Plasma chemistry must be matched to target substrate; different gases for Si, SiO₂, Si₃N₄, metal layers.
• Ion energy tuning balances etch rate, sidewall roughness and mask erosion.
• Heat management is critical; high-energy plasma may cause wafer thermal deformation or photoresist burnout.
• Cost of ownership is higher than wet etching; vacuum equipment and gas consumables increase production expense.
• Mask selection: Hard masks are often required for deep etch, as photoresist may degrade under strong plasma bombardment.