What Is Etching Process in Semiconductor

Etching is one of the most critical core unit processes in semiconductor wafer fabrication. After photolithography transfers circuit patterns onto photoresist layers, semiconductor etching selectively removes unwanted thinfilm materials from wafer surfaces, reproducing accurate micronano circuit structures beneath the photoresist mask. In short, photolithography draws the blueprint, and etching carves the real physical circuits on silicon wafers. Without highprecision etching technology, modern nanometerlevel chip manufacturing would be impossible.

Semiconductor etching can be divided into two major technical routes: wet chemical etching and dry plasma etching. They differ greatly in working principle, anisotropy, feature size capability and application scenarios. Chip fabs deploy both processes according to different film layers, pattern dimensions and production requirements.

1. Wet Etching in Semiconductor Manufacturing

Semiconductor wet etching uses liquid chemical etchant to dissolve exposed thinfilm materials on wafers through chemical reaction. The wafer is immersed in or sprayed with specific corrosive solution. Material removal happens in all directions, presenting isotropic etching characteristics, which means vertical and lateral etching rates are nearly equal. Significant undercut will occur under the photoresist mask.

Due to obvious side undercut effect, traditional wet etching cannot satisfy nanoscale ultrafine pattern requirements. It is mainly applied for relatively largesize structures, blanket film stripping, surface cleaning and damage removal in semiconductor production. Typical use cases include silicon dioxide layer stripping before special processes, metal layer removal, wafer surface residue cleaning and sacrificiallayer release for MEMS devices.

Wet etching owns unique advantages: simple equipment, high throughput, relatively low cost and low plasmainduced damage to wafers. Nevertheless, its isotropic nature sets hard limits for advancednode chips. For circuits below 3 μm feature size, pure wet etching gradually steps back from main patterndefinition procedures. Even so, wetetchingbased photochemical machining still plays an important supporting role in semiconductor packaging, for manufacturing metal masks, ball masks, flux masks and shielding components for chip assembly.

2. Dry Plasma Etching — Dominant Etching for Advanced Semiconductor Nodes

Dry etching, also named plasma etching, is the mainstream etching technology for modern advancednode semiconductor chips. The whole reaction proceeds inside a highvacuum reaction chamber. Reactive process gas is injected, then excited into highenergy plasma by radiofrequency power supply. Plasma contains large numbers of ions, free radicals and reactive neutral particles.

Dry etching combines two kinds of materialremoval mechanisms: physical ion bombardment and chemical radical reaction. Under biasvoltage control, positive ions strike the wafer surface vertically. The vertical bombardment greatly accelerates vertical etching rate while suppressing lateral erosion. This creates highly anisotropic etching profiles, forming nearvertical sidewalls for tiny grooves and contact holes, with minimal undercut underneath mask layers. This is exactly what nanoscale chip patterning demands.

According to practical application categories, dry etching further breaks down into reactive ion etching (RIE), deep reactive ion etching (DRIE), inductively coupled plasma etching (ICP) and other subtypes. Different hardware configurations are selected for silicon etching, dielectric etching and metal etching respectively.

Typical DryEtching Workflow inside Semiconductor Fab

Wafer loading: The patterned wafer after photolithography is transferred into vacuum etching chamber. Strict particlefree environment is required to avoid circuit defects.

Chamber vacuum pumping: Air inside reaction chamber is evacuated to reach specified highvacuum condition.

Processgas inlet: Corresponding reactive gas mixes and flows into chamber, matched with target thinfilm material (silicon, SiO₂, SiN, metal etc.).

Plasma ignition: RF power activates gas to generate dense plasma. Ions accelerate vertically toward wafer surface under electricfield bias.

Selective material removal: Physical bombardment plus chemical reaction etch away exposed thinfilm material. Maskcovered regions remain intact. Realtime endpoint detector monitors etching depth and film status.

Chamber purging: Cut off gas source, purge residual reaction byproduct gas out of chamber.

Wafer unloading: Completed wafer is delivered out for subsequent cleaning process.

Three core performance indicators judge semiconductor etching quality: selectivity, anisotropy and uniformity.

Selectivity: The ratio between etching rate of target film and mask / underlying layer etching rate. High selectivity ensures we etch off desired material while barely consuming photoresist mask or damaging the underlayer film. Poor selectivity will cause mask loss or substrate overetching.

Anisotropy: Reflects sidewall verticality. High anisotropy produces straight sidewalls, which is essential for ultrasmall contact holes and narrow circuit lines.

Withinwafer uniformity: Etching rate keeps consistent across the whole wafer surface, preventing partial overetching or underetching on largediameter 200 mm / 300 mm wafers.

Typical Application Scenarios for Semiconductor Etching

Frontend wafer fabrication: Dry plasma etching defines transistor structures, etches shallowtrench isolation (STI), forms contact holes and via holes, patterns metal interconnect layers, etches silicon nitride and silicon oxide dielectric films. Almost every layer of chip circuit needs dryetch processing.

MEMS & sensor chips: DRIE deep silicon etching creates deep silicon cavities, throughsilicon vias (TSV) and complex micromechanical structures. Both dry and wet etching are widely adopted.

Semiconductor packaging field: At backend packaging stage, apart from waferlevel dry etching, wetbased photochemical etching manufactures various precision metal auxiliary components, including ball mask, flux mask, lead frame and micro shielding parts for chip packaging equipment. These packaging metal parts require burrfree, stressfree microapertures, where chemical etching shows prominent advantages over laser or stamping.

Difference Between Frontend Wafer Etching and Packagingstage Chemical Etching

Many people confuse semiconductor frontend dry plasma etching with packagingoriented metal chemical etching. Frontend dry plasma etching works on siliconbased thin films inside vacuum chambers, pursuing nanometerscale anisotropic patterns for chip circuits. Packagingside chemical etching belongs to wet subtractive manufacturing for metal sheets, producing hardware masks and structural components for chip assembly. They serve different links of the semiconductor industrial chain, though both belong to the broad “etching” concept.

Summary

To conclude what etching process means in semiconductor: it is the patterncarving step following photolithography. Wet etching features isotropic material removal, mainly used for cleaning, stripping and MEMS sacrificial release. Dry plasma etching provides highanisotropy nanoscale patterning and becomes the core etching solution for advancednode wafer fabrication. Etching performance directly determines circuit dimensional accuracy, sidewall profile and final chip yield. Meanwhile, derivative chemical etching technology delivers indispensable precision metal parts for semiconductor backend packaging manufacturing.