In the realm of advanced semiconductor packaging, as the density of flip chip, wafer-level packaging, and system-in-package continues to rise, precise flux application has become a critical step ensuring soldering reliability. A flux carrier plate, also referred to as a flux dipping plate or flux transfer plate, is the core precision tooling that enables uniform application of flux to millions of micron-scale bumps. The plate surface features hundreds of thousands or even millions of micro-cavities that perfectly match the chip bump array, capable of transferring a defined amount of flux accurately onto each solder ball, thereby eliminating bridging and void defects. Electroforming, with its sub-micron replication fidelity and extreme design freedom, has become the process of choice for manufacturing high-performance flux carrier plates. This article details the full electroforming process flow of flux carrier plates and outlines their main application fields.

#### 1. Core Requirements of Flux Carrier Plates and the Advantages of Electroforming

Flux carrier plates must simultaneously offer extremely high positional accuracy, consistent cavity depth, and superior surface quality. Typical cavity depths range from 15 μm to 50 μm, with positional tolerances required within ±2 μm, while depth uniformity across the entire working area must be controlled to within ±1.5 μm. Laser machining and mechanical engraving struggle to simultaneously meet density, accuracy, and bottom finish requirements at such minute scales. The electroforming process, by atomically depositing metal ions onto a precision mandrel, can perfectly replicate the mandrel's microscopic topography without stress accumulation. The resulting nickel or nickel-alloy carrier plates exhibit a hardness of 450-550 HV and strong corrosion resistance, withstanding repeated contact with flux and cleaning solvents, thus delivering a service life far exceeding that of products made by other processes.

#### 2. Full Electroforming Process Flow for Flux Carrier Plates

The electroforming of flux carrier plates belongs to the high-end precision electroforming category, typically involving the following six core steps.

**1. Mandrel Design and Lithographic Patterning**  

The mandrel defines the final cavity geometry. First, a thick photoresist layer, such as SU-8 negative photoresist, is spin-coated onto a glass or silicon substrate. Using a high-precision direct-write lithography system or a stepper, the designed bump array pattern is accurately transferred onto the resist layer. After development, a micro-pillar structured resist mandrel is formed. The diameter, height, and pitch of these pillars directly correspond to the dimensions of the carrier plate cavities. To achieve exceptional uniformity, the lithography process must be carried out in a Class 100 cleanroom environment, with closed-loop control over exposure dose and development time.

**2. Conductive Treatment**  

Since the photoresist is non-conductive, an ultra-thin conductive layer must be deposited onto the mandrel surface. Magnetron sputtering or vacuum evaporation is commonly employed, depositing approximately 10 nm of titanium or chromium as an adhesion layer, followed by a 50-100 nm gold or nickel conductive seed layer. This seed layer must be continuous and uniformly cover the sidewalls and bottoms of the micro-pillars; otherwise, uneven electrodeposition will occur, leading to voids or cavity depth variations. Shadowing effects during sputtering are compensated for by rotating the substrate stage.

**3. Electrodeposition**  

The prepared mandrel is immersed in a nickel sulfamate electroforming solution and connected to a DC or pulse power supply. Nickel sulfamate baths offer low internal stress, preventing warpage over large-area electroforming. To achieve precise micron-scale cavity depth, current density is tightly controlled, typically between 1 and 5 A/dm², supported by continuous filtration and constant temperature control. Pulse electroforming techniques further enhance the packing density of metal between the pillars and eliminate pinholes at the cavity bottom. The deposit thickness is monitored in real time via an ampere-hour meter; once the metal layer surpasses the mandrel pillar height and reaches the designed backplate thickness, electrodeposition stops. The final nickel or nickel-cobalt alloy layer integrates both the micro-cavity working surface and a rigid support backplate, with an overall thickness typically between 0.3 mm and 1.0 mm.

**4. Demolding and Separation**  

After electroforming, the entire assembly is removed from the bath and cleaned. The metal carrier plate is separated from the glass or silicon mandrel through mechanical peeling or thermal demolding, which leverages differences in thermal expansion coefficients. Some processes employ chemical etching to remove the remaining photoresist pillars, yielding clean micro-cavity arrays. The edges of the demolded plate are mechanically trimmed to create a flat profile.

**5. Post-processing and Surface Modification**  

To reduce the adhesion between the flux and the carrier plate surface and improve the transfer release characteristics, the cavity region undergoes a low-surface-energy treatment. Common processes involve forming a self-assembled fluorosilane monolayer or applying a Teflon-like nano-coating. These coatings, only tens of nanometers thick, do not alter cavity dimensions but significantly increase the contact angle, ensuring the flux can completely detach from the cavity and transfer onto the bump. After treatment, the plates undergo 100% automated optical inspection in a clean environment, measuring the depth and diameter of each cavity to eliminate any anomalies.

**6. Precision Metrology and Final Inspection**  

Final quality inspection uses white-light interferometry or confocal microscopy to scan the full-plate depth and profile data, verifying that all cavity depths fall within the process window. Simultaneously, a coordinate measuring machine checks overall flatness and plate thickness to ensure a perfect match with the vacuum chuck surface of the placement equipment. Only plates passing all metrology steps proceed to cleanroom packaging and delivery to the semiconductor packaging line.

#### 3. Main Application Fields of Flux Carrier Plates

**1. Flip Chip Packaging**  

This is the largest application area for flux carrier plates. Whether in FCBGA or FCCSP packages, customized electroformed carrier plates are essential for the flux dipping process of chip micro-bumps. They can apply a precisely thickness-controlled flux film across tens of thousands of copper pillar bumps or solder bumps on an entire chip in a single step, preventing non-wetting or bridging failures during reflow attachment.

**2. Wafer-Level Packaging**  

In fan-out wafer-level packaging and 2.5D interposer packaging, the carrier plate area is larger and the bump pitch is finer. Electroformed carrier plates can provide panel-level dipping capability up to 600 mm × 600 mm, adapting to the trend of large-format packaging and ensuring uniform flux transfer volume across the entire panel, laying the yield foundation for multi-chip heterogeneous integration.

**3. System-in-Package and MEMS Assembly**  

SiP modules often contain a mix of passive components and bare dice with varying bump heights. By employing a segmented depth design, electroformed carrier plates can machine cavities of different depths in different regions, enabling differentiated flux transfer volumes. This accommodates uneven soldering height requirements, greatly expanding the application range of automated assembly. In hermetic packaging for MEMS devices, electroformed flux carrier plates are similarly used for pre-application of flux on high-precision solder seal rings.

**4. Optoelectronic and RF Modules**  

High-speed optical modules and millimeter-wave RF front-ends demand micro-bump interconnects with extremely high alignment accuracy. The sub-micron alignment fiducial marks on an electroformed flux carrier plate are directly formed together with the mandrel during electroforming, enabling perfect alignment with reference marks on the chip. This provides a reliable flux transfer method for advanced processes like co-packaged optics.

With their irreplaceable precision advantages and material properties, electroformed flux carrier plates have become deeply embedded in the modern semiconductor packaging supply chain. As chip interconnect density continues to shrink and 3D stacked packaging becomes widespread, electroforming technology will evolve toward larger areas, smaller cavities, and multi-functional integration, continuing to support the high-reliability and high-yield targets of next-generation microelectronic assembly.